In this contribution we presented the implementation of a tapped-delay-line (TDL) TDC with 8-channels in a Xilinx Kintex-7 FPGA device with r.m.s. value of the resolution around 20 ps. Main features of the instrument are the resource-saving and low-power architecture, the presence of an edge detector able to sense the position of the transition propagating along the delay line within one clock cycle, the interface through a USB 3.0 communication gate.

8-Channels high-resolution TDC in FPGA

Lusardi, Nicola;Geraci, Angelo
2015-01-01

Abstract

In this contribution we presented the implementation of a tapped-delay-line (TDL) TDC with 8-channels in a Xilinx Kintex-7 FPGA device with r.m.s. value of the resolution around 20 ps. Main features of the instrument are the resource-saving and low-power architecture, the presence of an edge detector able to sense the position of the transition propagating along the delay line within one clock cycle, the interface through a USB 3.0 communication gate.
2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2015
9781467398626
Nuclear and High Energy Physics; Radiology, Nuclear Medicine and Imaging; Instrumentation
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1035482
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