High performance Storage Class Memories could benefit from a fast decoding Error Correcting Code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents from adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore we propose an architecture for fast decoding of double-and triple-error correcting codes. In our architecture any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular the Error Locator Polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here we describe a gate level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation.

Fast Decoding ECC for future memories

BELLINI, SANDRO;FERRARI, MARCO PIETRO;TOMASONI, ALESSANDRO
2016-01-01

Abstract

High performance Storage Class Memories could benefit from a fast decoding Error Correcting Code (ECC), able to correct a few errors in just a few nanoseconds. The class of BCH codes provides excellent candidates to play this role. The low latency requirement prevents from adopting iterative or sequential processes in the encoding and decoding phases-as traditionally done for storage application based on Flash NAND technology. Therefore we propose an architecture for fast decoding of double-and triple-error correcting codes. In our architecture any time-consuming iterative computation is eliminated, and the most complex evaluations are isolated and carried in parallel with the other terms, to avoid bottlenecks in the decoder. In particular the Error Locator Polynomial is computed by a combinatorial logic, and its roots are searched by testing all the bits simultaneously. Here we describe a gate level design of these architectures. We also give an in-depth analysis of hardware-oriented implementations of finite field operations, and of bases for element representation.
Block codes; DRAM; Error correction codes; Galois fields; Nonvolatile memory; Phase change memory; Computer Networks and Communications; Electrical and Electronic Engineering
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1010014
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