This work presents the first experimental results of SFERA, a multichannel low-noise readout ASIC designed for both X and γ-ray detectors for spectroscopy and imaging applications. The chip has been developed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of silicon drift detectors (SDDs), although the ASIC may find a wider application also with other detector solutions. The chip is able to accommodate five different energy ranges: 10, 16, 36 and 50 keV for X-ray photons and a maximum of 20000 e- in the case of scintillation light detection. Filters peaking-times are programmable among 0.5, 1, 2,3, 4 and 6 μs. The analog section of the IC comprises a bank of 16 readout channels made of 9th order semi-Gaussian shaping-amplifiers followed by peak detectors (PKS), while a digital logic section synchronizes PKS phases, operates pile-up rejection and drives the multiplexer (MUX). Three different data multiplexing strategies are implemented: the so-called polling X, for highrate applications, the polling γ, for γ-ray detection and finally the sparse readout, used for signals derandomization purposes in conjunction with a dedicated channel-address logic. A successive-approximation-register (SAR) ADC has also been integrated to eventually digitize the output MUX data. The technology is AMS 0.35 μm CMOS and the chip area occupancy is 25 mm2. After a brief description of the circuit, the first experimental results, including X-ray spectroscopy measurements using SDDs and CUBE preamplifiers are presented.

SFERA: A general purpose readout IC for X and γ-ray detectors

SCHEMBARI, FILIPPO;QUAGLIA, RICCARDO;BELLOTTI, GIOVANNI;FIORINI, CARLO ETTORE
2015

Abstract

This work presents the first experimental results of SFERA, a multichannel low-noise readout ASIC designed for both X and γ-ray detectors for spectroscopy and imaging applications. The chip has been developed to process signals coming from solid-state detectors and CMOS preamplifiers. The design has been guided by the use of silicon drift detectors (SDDs), although the ASIC may find a wider application also with other detector solutions. The chip is able to accommodate five different energy ranges: 10, 16, 36 and 50 keV for X-ray photons and a maximum of 20000 e- in the case of scintillation light detection. Filters peaking-times are programmable among 0.5, 1, 2,3, 4 and 6 μs. The analog section of the IC comprises a bank of 16 readout channels made of 9th order semi-Gaussian shaping-amplifiers followed by peak detectors (PKS), while a digital logic section synchronizes PKS phases, operates pile-up rejection and drives the multiplexer (MUX). Three different data multiplexing strategies are implemented: the so-called polling X, for highrate applications, the polling γ, for γ-ray detection and finally the sparse readout, used for signals derandomization purposes in conjunction with a dedicated channel-address logic. A successive-approximation-register (SAR) ADC has also been integrated to eventually digitize the output MUX data. The technology is AMS 0.35 μm CMOS and the chip area occupancy is 25 mm2. After a brief description of the circuit, the first experimental results, including X-ray spectroscopy measurements using SDDs and CUBE preamplifiers are presented.
2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2015
IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD
9781467398626
9781467398626
Nuclear and High Energy Physics; Radiology, Nuclear Medicine and Imaging; Instrumentation, sezele
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1009966
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