A 12-bit analog-to-digital converter (ADC) addressed to Silicon-Drift Detectors (SDDs) multichannel readout ASICs for X- and gamma-ray applications is presented. Aiming at digitizing output multiplexed data from the upstream analog filters banks, the converter must ensure 11-bit accuracy and a sampling frequency of about 5 MS/s. The ADC architecture is the charge-redistribution (CR) successive-approximation register (SAR). A fully differential topology has also been chosen for better rejection of common-mode noise and disturbances. The internal DAC is made of binary-scaled capacitors, whose bottom plates are switched by the SAR logic to perform the binary search of the analog input value by means of the monotonic switching scheme. The A/D converter is integrated on SFERA, a multichannel ASIC fabricated in a standard CMOS 0.35 μm 3.3 V technology and it occupies an area of 0.42 mm2. Simulated static performance shows monotonicity over the whole input-output characteristic. The description of the circuit topology and of inner blocks architectures together with the experimental characterization is here presented.

A 12-bit SAR ADC integrated on a multichannel silicon drift detector readout IC

SCHEMBARI, FILIPPO;BELLOTTI, GIOVANNI;FIORINI, CARLO ETTORE
2016

Abstract

A 12-bit analog-to-digital converter (ADC) addressed to Silicon-Drift Detectors (SDDs) multichannel readout ASICs for X- and gamma-ray applications is presented. Aiming at digitizing output multiplexed data from the upstream analog filters banks, the converter must ensure 11-bit accuracy and a sampling frequency of about 5 MS/s. The ADC architecture is the charge-redistribution (CR) successive-approximation register (SAR). A fully differential topology has also been chosen for better rejection of common-mode noise and disturbances. The internal DAC is made of binary-scaled capacitors, whose bottom plates are switched by the SAR logic to perform the binary search of the analog input value by means of the monotonic switching scheme. The A/D converter is integrated on SFERA, a multichannel ASIC fabricated in a standard CMOS 0.35 μm 3.3 V technology and it occupies an area of 0.42 mm2. Simulated static performance shows monotonicity over the whole input-output characteristic. The description of the circuit topology and of inner blocks architectures together with the experimental characterization is here presented.
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1009927
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