A novel architecture for digital lock-in amplifiers (LIAs) able to overcome the resolution limit of standards implementations is proposed. The slow gain fluctuations of both the DAC and ADC of the generation and acquisition stages of the LIA are compensated using two ADCs alternately acquiring the signal coming from the device under test (DUT) and the stimulus (STIM) signal. Experimental results demonstrate a resolution enhancement of more than an order of magnitude with respect to state of art LIAs, enabling sub-ppm resolution measurements with an instrument working up to 5 MHz without imposing any constraint to the DUT or to the experimental setup.

A General Purpose Lock-In Amplifier Enabling Sub-ppm Resolution

GERVASONI, GIACOMO;CARMINATI, MARCO;FERRARI, GIORGIO
2016

Abstract

A novel architecture for digital lock-in amplifiers (LIAs) able to overcome the resolution limit of standards implementations is proposed. The slow gain fluctuations of both the DAC and ADC of the generation and acquisition stages of the LIA are compensated using two ADCs alternately acquiring the signal coming from the device under test (DUT) and the stimulus (STIM) signal. Experimental results demonstrate a resolution enhancement of more than an order of magnitude with respect to state of art LIAs, enabling sub-ppm resolution measurements with an instrument working up to 5 MHz without imposing any constraint to the DUT or to the experimental setup.
Procedia Engineering
FPGA; Lock-in amplifier; low-noise; ppm resolution; sensors; Engineering (all)
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11311/1009846
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