This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity. It will be also demonstrated that this property can be generalized to the case of PLLs based on coarse time-to-digital converters with mid- rise quantization, whose adoption speeds up lock transients. The results are assessed in a fabricated 3.6-GHz fractional-N digital phase-locked loop.

Bang-Bang Digital PLLs

LEVANTINO, SALVATORE
2016-01-01

Abstract

This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity. It will be also demonstrated that this property can be generalized to the case of PLLs based on coarse time-to-digital converters with mid- rise quantization, whose adoption speeds up lock transients. The results are assessed in a fabricated 3.6-GHz fractional-N digital phase-locked loop.
2016
European Solid-State Circuits Conference (ESSCIRC), ESSCIRC 2016 - 42nd
978-1-5090-2972-3
sezele
PLL, CMOS, Wireless, Quantisation, IC
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/1002924
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