SANTAMBROGIO, MARCO DOMENICO
 Distribuzione geografica
Continente #
NA - Nord America 4.880
EU - Europa 4.769
AS - Asia 2.683
AF - Africa 230
SA - Sud America 105
OC - Oceania 75
Continente sconosciuto - Info sul continente non disponibili 15
Totale 12.757
Nazione #
US - Stati Uniti d'America 4.622
IT - Italia 1.838
CN - Cina 591
IN - India 527
DE - Germania 456
FR - Francia 455
GB - Regno Unito 316
HK - Hong Kong 238
NL - Olanda 233
CA - Canada 204
RU - Federazione Russa 196
JP - Giappone 178
CH - Svizzera 171
CZ - Repubblica Ceca 154
KR - Corea 151
TW - Taiwan 140
IR - Iran 129
SG - Singapore 121
ES - Italia 102
VN - Vietnam 99
UA - Ucraina 98
GR - Grecia 96
IL - Israele 73
BE - Belgio 71
RO - Romania 70
TR - Turchia 68
AU - Australia 67
IE - Irlanda 63
FI - Finlandia 57
PL - Polonia 56
SE - Svezia 54
PK - Pakistan 53
MY - Malesia 52
ID - Indonesia 47
AT - Austria 46
DZ - Algeria 46
EG - Egitto 46
PT - Portogallo 44
TH - Thailandia 44
ZA - Sudafrica 43
MX - Messico 41
BR - Brasile 39
SA - Arabia Saudita 38
DK - Danimarca 33
TN - Tunisia 32
PH - Filippine 30
LT - Lituania 29
MA - Marocco 24
AR - Argentina 21
HU - Ungheria 20
NO - Norvegia 20
SI - Slovenia 17
CL - Cile 16
MN - Mongolia 16
BG - Bulgaria 14
KZ - Kazakistan 14
ET - Etiopia 13
NG - Nigeria 13
BY - Bielorussia 12
IQ - Iraq 10
RS - Serbia 10
EC - Ecuador 9
EU - Europa 9
BD - Bangladesh 8
CO - Colombia 8
JO - Giordania 8
NZ - Nuova Zelanda 8
HR - Croazia 7
PE - Perù 7
SK - Slovacchia (Repubblica Slovacca) 7
BJ - Benin 6
LK - Sri Lanka 6
NP - Nepal 6
AE - Emirati Arabi Uniti 5
AL - Albania 5
GE - Georgia 5
KW - Kuwait 5
LB - Libano 5
SV - El Salvador 5
SY - Repubblica araba siriana 5
BA - Bosnia-Erzegovina 4
MK - Macedonia 4
UY - Uruguay 4
A2 - ???statistics.table.value.countryCode.A2??? 3
CM - Camerun 3
EE - Estonia 3
HN - Honduras 3
LU - Lussemburgo 3
QA - Qatar 3
CR - Costa Rica 2
CU - Cuba 2
CY - Cipro 2
GH - Ghana 2
LV - Lettonia 2
PS - Palestinian Territory 2
XK - ???statistics.table.value.countryCode.XK??? 2
A1 - Anonimo 1
AM - Armenia 1
BO - Bolivia 1
BT - Bhutan 1
Totale 12.749
Città #
Houston 473
Milan 396
Ashburn 319
Fairfield 274
Ann Arbor 262
Buffalo 191
Seattle 184
Santa Cruz 171
Woodbridge 160
Beijing 155
Cambridge 123
Wilmington 104
Bengaluru 92
Zurich 90
Los Angeles 86
Central 83
Boardman 82
Rome 82
Paris 74
Taipei 74
Dublin 63
Chicago 62
Shanghai 62
San Jose 59
Mountain View 53
Falls Church 52
Moscow 52
Singapore 51
Tokyo 51
London 45
Dong Ket 44
Hangzhou 44
Toronto 44
Las Vegas 43
Turin 43
Athens 41
Bari 41
Ottawa 39
San Diego 38
Chennai 35
Varese 35
Amsterdam 32
Hyderabad 32
Mumbai 31
Bangkok 28
New York 28
Palermo 28
San Francisco 28
Wuhan 28
Delft 27
Frankfurt am Main 27
Tehran 27
Nanjing 26
Hanoi 25
Helsinki 25
Sydney 25
Gurgaon 24
Jakarta 24
Atlanta 23
Bangalore 23
Berlin 23
Hong Kong 23
Muizenberg 23
Vienna 23
Duncan 22
New Delhi 22
Redmond 22
Shenzhen 22
Central District 21
Charlottesville 21
Florence 21
Munich 21
Sunnyvale 21
Boulder 20
Cairo 20
Clearwater 20
Irvine 20
Istanbul 20
Phoenix 20
Fleming Island 19
Grenoble 19
Guangzhou 19
Montréal 19
Padova 19
Seoul 19
Boston 18
Melbourne 18
Seongnam-si 18
Ankara 17
Bresso 16
Kolkata 16
Lisbon 16
Rotterdam 16
Salerno 16
Ulaanbaatar 16
University Park 16
Vedano al Lambro 16
Ho Chi Minh City 15
Tel Aviv 15
Delhi 14
Totale 5.745
Nome #
On how to extract breathing rate from PPG signal using wearable devices, file e0c31c09-6d7c-4599-e053-1705fe0aef77 2.881
Fast and Accurate Entity Linking via Graph Embedding, file e0c31c0e-a33d-4599-e053-1705fe0aef77 836
FPGA-based Embedded System Implementation of Audio Signal Alignment, file e0c31c0f-c643-4599-e053-1705fe0aef77 571
Pushing the Level of Abstraction of Digital System Design: a Survey on How to Program FPGAs, file e3b8d0bb-125b-4457-9780-250f72ef7a02 494
A Framework for Customizable FPGA-based Image Registration Accelerators, file e0c31c11-0e69-4599-e053-1705fe0aef77 450
CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching, file e0c31c11-69dc-4599-e053-1705fe0aef77 445
Enabling Transparent Hardware Acceleration on Zynq SoC for Scientific Computing, file e0c31c0f-da82-4599-e053-1705fe0aef77 391
BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systems, file e0c31c0f-ba41-4599-e053-1705fe0aef77 345
A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures, file e0c31c09-6a0c-4599-e053-1705fe0aef77 306
Building High-Performance, Easy-to-use Polymorphic Parallel Memories with HLS, file e0c31c0f-c63b-4599-e053-1705fe0aef77 304
On how to accelerate iterative stencil loops: A scalable streaming-based approach, file e0c31c0e-be75-4599-e053-1705fe0aef77 302
On Power and Energy Consumption Modeling for Smart Mobile Devices, file e0c31c08-77b6-4599-e053-1705fe0aef77 301
Danger-system: Exploring new ways to manage occupants safety in smart building, file e0c31c09-6d75-4599-e053-1705fe0aef77 292
An Energy-Efficient Domain-Specific Architecture for Regular Expressions, file e0c31c12-5dd6-4599-e053-1705fe0aef77 277
A Comprehensive Methodology to Optimize FPGA Designs via the Roofline Model, file e0c31c12-3ea4-4599-e053-1705fe0aef77 250
Hardware resources analysis of BNNs splitting for FARD-based multi-FPGAs Distributed Systems, file e0c31c0f-c48e-4599-e053-1705fe0aef77 245
Dovado: An Open-Source Design Space Exploration Framework, file e0c31c11-c0b5-4599-e053-1705fe0aef77 231
cODA: An Open-Source Framework to Easily Design Context-Aware Android Apps, file e0c31c08-634d-4599-e053-1705fe0aef77 224
Faber: a Hardware/Software Toolchain for Image Registration, file b7a401ca-75bd-4e7c-b559-226c48080583 223
Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems, file e0c31c09-6a0a-4599-e053-1705fe0aef77 222
K-Ways Partitioning of Polyhedral Process Networks: A Multi-level Approach, file e0c31c09-6d79-4599-e053-1705fe0aef77 209
FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration, file e0c31c09-6dba-4599-e053-1705fe0aef77 206
Power-awareness and smart-resource management in embedded computing systems, file e0c31c09-6d72-4599-e053-1705fe0aef77 202
Pareto Optimal Design Space Exploration for Accelerated CNN on FPGA, file e0c31c0f-c645-4599-e053-1705fe0aef77 189
A hardware approach to protein identification, file e0c31c09-6d7e-4599-e053-1705fe0aef77 186
OpenMPower: An Open and Accessible Database About Real World Mobile Devices, file e0c31c08-77b4-4599-e053-1705fe0aef77 175
A Performance-Aware Quality of Service-Driven Scheduler for Multicore Processors, file e0c31c08-9496-4599-e053-1705fe0aef77 173
Design Methodologies for Reconfigurable NoC-based Embedded Systems, file e0c31c08-db65-4599-e053-1705fe0aef77 156
Thermal-aware floorplanning for partially-reconfigurable FPGA-based systems, file e0c31c09-6d76-4599-e053-1705fe0aef77 155
R3TOS-Based Autonomous Fault-Tolerant Systems, file e0c31c0d-e5a8-4599-e053-1705fe0aef77 153
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs, file e0c31c09-2e6d-4599-e053-1705fe0aef77 147
Power consumption models for multi-tenant server infrastructures, file e0c31c0b-cddc-4599-e053-1705fe0aef77 143
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation, file e0c31c0e-d110-4599-e053-1705fe0aef77 115
EMPhASIS: An EMbedded Public Attention Stress Identification System, file e0c31c0f-da83-4599-e053-1705fe0aef77 114
A Case Study for an Accelerated DCNN on FPGA-based Embedded Distributed System, file e0c31c0f-c640-4599-e053-1705fe0aef77 112
EXTRA: Towards an efficient open platform for reconfigurable High Performance Computing, file e0c31c09-6d77-4599-e053-1705fe0aef77 106
Quality of Service Driven Runtime Resource Allocation in Reconfigurable HPC Architectures, file e0c31c0c-117a-4599-e053-1705fe0aef77 97
ATHENA: a GPU-based Framework for Biomedical 3D Rigid Image Registration, file 67affaa1-c541-4be4-9d58-99fc62098273 93
Sex Differences in the ECG Interpretation: A Functional Data Analysis Perspective, file e0c31c12-42b8-4599-e053-1705fe0aef77 93
Characterizing Molecular Dynamics Simulation on Commodity Platforms, file 117324d8-9845-4196-b757-ac78b1f0e609 78
A software cache partitioning system for hash-based caches, file e0c31c11-1eba-4599-e053-1705fe0aef77 64
A Functional Data Analysis Approach to Left Ventricular Remodeling Assessment, file e0c31c12-3c88-4599-e053-1705fe0aef77 59
Math Skills: a New Look from Functional Data Analysis, file e1f5cc45-79db-4022-a9d3-c12ce654fffc 58
Coordination of Independent Loops in Self-Adaptive Systems, file e0c31c0d-3759-4599-e053-1705fe0aef77 42
YARB: a Methodology to Characterize Regular Expression Matching on Heterogeneous Systems, file 33b98e88-2d56-41ec-b312-c69b7aca943e 40
A Bird’s Eye View on Quantum Computing: Current and Future Trends, file 686086ac-f535-4b4c-b40d-377f278864dc 39
Enabling Efficient Regular Expression Matching at the Edge through Domain-Specific Architectures, file ba3070ed-ae6d-4cf6-ac1f-a5774c29b36b 39
A runtime controller for openCL applications on heterogeneous system architectures, file e0c31c0e-ea38-4599-e053-1705fe0aef77 38
On How to Unravel Bone Microscale Phenomena: A Mask-Guided Attention SR-microCT Image Classification Approach, file b4ddfb0a-ed84-449d-9738-f67a3c06f4b6 36
Automated Fine-Grained CPU Provisioning for Virtual Machines, file e0c31c0d-9adb-4599-e053-1705fe0aef77 36
METHOD FOR LOCATING A DEVICE INSIDE AN AREA, file e0c31c0f-2d67-4599-e053-1705fe0aef77 36
Power consumption management under a low-level performance constraint in the Xen hypervisor, file e0c31c0f-e77a-4599-e053-1705fe0aef77 32
BEBOP: Bidirectional dEep Brain cOnnectivity maPping, file e254fe92-5df1-4195-8c40-652ef78855a2 31
FARD: Accelerating Distributed Fog Computing Workloads through Embedded FPGAs, file e0c31c0f-e293-4599-e053-1705fe0aef77 29
Toward smart building design automation: Extensible CAD framework for indoor localization systems deployment, file e0c31c11-c90a-4599-e053-1705fe0aef77 25
A Run-Time System for Partially Reconfigurable FPGAs: The case of STMicroelectronics SPEAr board, file e0c31c09-6a08-4599-e053-1705fe0aef77 17
Improving the security and the scalability of the AES algorithm, file e0c31c08-56ce-4599-e053-1705fe0aef77 16
On the Design and Characterization of Set Packing Problem on Quantum Annealers, file 305cf765-55ea-4f7c-bd86-278845ef4e2c 15
BlastFunction: A Full-stack Framework Bringing FPGA Hardware Acceleration to Cloud-native Applications, file e0c31c12-84ee-4599-e053-1705fe0aef77 10
MARC: A resource consumption modeling service for self-aware autonomous agents, file e0c31c0b-c120-4599-e053-1705fe0aef77 8
Starlight: A kernel optimizer for GPU processing, file be595586-a175-403a-bc3f-6e419244a36d 7
Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach, file e0c31c08-234d-4599-e053-1705fe0aef77 6
On how to accelerate iterative stencil loops: A scalable streaming-based approach, file e0c31c0a-0b83-4599-e053-1705fe0aef77 5
Toward smart building design automation: Extensible CAD framework for indoor localization systems deployment, file e0c31c0f-0c8e-4599-e053-1705fe0aef77 5
Anatomically compliant modes of variations: New tools for brain connectivity, file 012eb4cf-c01a-44f5-a07c-4a5f2c148177 4
BrainTrack: A Replicable and Accessible Methodology for Customized Brain-Machine Interface Applications, file 713bd448-9d3c-4ec8-98c4-ef26ef79a30b 4
Audio Source Localization Using Multi-Microphone Techniques, file e0c31c07-e9f2-4599-e053-1705fe0aef77 3
Automated Fine-Grained CPU Provisioning for Virtual Machines, file e0c31c0a-0b8e-4599-e053-1705fe0aef77 3
A faster approach to ECG analysis in emergency situations, file e0c31c0f-c9a5-4599-e053-1705fe0aef77 3
Leveraging succinct data structures for DNA sequence mapping on FPGA, file e0c31c11-57e6-4599-e053-1705fe0aef77 3
Plaster: An Embedded FPGA-based Cluster Orchestrator for Accelerated Distributed Algorithms, file e0c31c12-3e21-4599-e053-1705fe0aef77 3
Large Forests and Where to “Partially” Fit Them, file e0c31c12-3e23-4599-e053-1705fe0aef77 3
Hephaestus: Codesigning and Automating 3D Image Registration on Reconfigurable Architectures, file 78ad4af7-bf13-4478-b210-d86a36a1d1bc 2
Coordination of Independent Loops in Self-Adaptive Systems, file e0c31c08-20f5-4599-e053-1705fe0aef77 2
Workload-aware power optimization strategy for asymmetric multiprocessors, file e0c31c09-e28f-4599-e053-1705fe0aef77 2
Autonomic thread scaling library for QoS management, file e0c31c0a-0a8b-4599-e053-1705fe0aef77 2
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops, file e0c31c0a-0a9b-4599-e053-1705fe0aef77 2
R3TOS-Based Autonomous Fault-Tolerant Systems, file e0c31c0a-0b42-4599-e053-1705fe0aef77 2
Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation, file e0c31c0a-8eb3-4599-e053-1705fe0aef77 2
Towards an automatic imaging biopsy of non-small cell lung cancer, file e0c31c0e-f7f3-4599-e053-1705fe0aef77 2
Diversity and inclusion: Buzzword or real value?, file e0c31c0f-2df4-4599-e053-1705fe0aef77 2
CircFA: A FPGA-based circular RNA aligner, file e0c31c0f-2f01-4599-e053-1705fe0aef77 2
High Level Specification of Embedded Listeners for Monitoring of Network-on-Chips, file e0c31c0f-9c28-4599-e053-1705fe0aef77 2
MARC: A resource consumption modeling service for self-aware autonomous agents, file e0c31c10-c130-4599-e053-1705fe0aef77 2
Towards Graph Machine Learning for Smart Grid Knowledge Graphs in Industrial Scenarios, file e0c31c12-387e-4599-e053-1705fe0aef77 2
Using Speculative Computation and Parallelizing Techniques to Improve Scheduling of Control based Designs, file e0c31c07-c1eb-4599-e053-1705fe0aef77 1
Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration, file e0c31c08-43ee-4599-e053-1705fe0aef77 1
An open-source, efficient and parameterizable hardware implementation of the AES algorithm, file e0c31c08-5b80-4599-e053-1705fe0aef77 1
Experimental evaluation and modeling of thermal phenomena on mobile devices, file e0c31c09-4b79-4599-e053-1705fe0aef77 1
Preemption-aware planning on Big-Data systems, file e0c31c0a-08f7-4599-e053-1705fe0aef77 1
PaRA-Sched: A Reconfiguration-Aware Scheduler for Reconfigurable Architectures, file e0c31c0a-0b8a-4599-e053-1705fe0aef77 1
On the automation of high level synthesis of convolutional neural networks, file e0c31c0a-0cfa-4599-e053-1705fe0aef77 1
ProFAX: A hardware acceleration of a protein folding algorithm, file e0c31c0b-27d4-4599-e053-1705fe0aef77 1
A highly scalable and efficient parallel design of N-body simulation on FPGA, file e0c31c0b-27d5-4599-e053-1705fe0aef77 1
Architectural optimizations for high performance and energy efficient Smith-Waterman implementation on FPGAs using OpenCL, file e0c31c0b-2966-4599-e053-1705fe0aef77 1
FFWD: Latency-Aware Event Stream Processing via Domain-Specific Load-Shedding Policies, file e0c31c0b-7e38-4599-e053-1705fe0aef77 1
Optimizing streaming stencil time-step designs via FPGA floorplanning, file e0c31c0b-a806-4599-e053-1705fe0aef77 1
FPGA-based PairHMM Forward Algorithm for DNA Variant Calling, file e0c31c0c-4204-4599-e053-1705fe0aef77 1
Five-point algorithm: An efficient cloud-based FPGA implementation, file e0c31c0c-787c-4599-e053-1705fe0aef77 1
HyPPO: Hybrid Performance-Aware Power-Capping Orchestrator, file e0c31c0c-dd70-4599-e053-1705fe0aef77 1
Totale 13.252
Categoria #
all - tutte 22.034
article - articoli 6.756
book - libri 0
conference - conferenze 14.911
curatela - curatele 0
other - altro 0
patent - brevetti 91
selected - selezionate 0
volume - volumi 276
Totale 44.068


Totale Lug Ago Sett Ott Nov Dic Gen Feb Mar Apr Mag Giu
2018/2019399 0 0 0 0 0 0 0 0 60 105 123 111
2019/20201.216 83 76 47 94 109 127 135 152 131 75 109 78
2020/20212.006 102 97 147 167 220 188 188 171 178 203 176 169
2021/20223.262 263 147 217 546 386 185 220 212 240 217 379 250
2022/20232.969 120 188 294 267 278 259 226 238 293 268 271 267
2023/20242.768 238 285 340 324 373 317 387 300 204 0 0 0
Totale 13.271