High-level power estimation of VLSI systems

The goal of this paper is to present an innovative conceptual framework suitable for achieving accurate and efficient estimation of power dissipation for data-path intensive architectures described at RT and Behavioral levels. The aim is to provide the designer with the capability of analyzing different solutions in the architectural design space, before the synthesis tasks. The proposed methodology addresses all the elements composing a typical data-path architecture, such as storage units, functional units and multiplexers. The paper includes experimental results demonstrating the validity of the proposed approach.