The paper presents a novel methodology for synthesizing PTL circuits, whose distinctive features are the use of a symbolic algorithm for the covering of the initial network in terms of PTL cells, and the exploitation of layout level area and delay model during the selection of the best covering solution. The results produced by the synthesis procedure on the full suite of the Iscas'85 combinational circuits are very encouraging.

Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits

FERRANDI, FABRIZIO;
1998-01-01

Abstract

The paper presents a novel methodology for synthesizing PTL circuits, whose distinctive features are the use of a symbolic algorithm for the covering of the initial network in terms of PTL cells, and the exploitation of layout level area and delay model during the selection of the best covering solution. The results produced by the synthesis procedure on the full suite of the Iscas'85 combinational circuits are very encouraging.
1998
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design - ICCAD '98
1581130082
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/665779
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