A new technique is described for modelling a general distributed RC line through a simple lumped net. This reduced order model approximates both the long time voltage response and the input loading effect of the line. The proposed method has the advantage of allowing the employment of circuit simulators such as SPICE to evaluate interconnect delays in complex layouts.
Efficient method for simulating time delays of distributed interconnections in VLSI circuits
MAFFEZZONI, PAOLO;BRAMBILLA, ANGELO MAURIZIO
1999-01-01
Abstract
A new technique is described for modelling a general distributed RC line through a simple lumped net. This reduced order model approximates both the long time voltage response and the input loading effect of the line. The proposed method has the advantage of allowing the employment of circuit simulators such as SPICE to evaluate interconnect delays in complex layouts.File in questo prodotto:
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