A synthesis methodology aimed at improving the quality of TSC devices

This paper proposes a synthesis methodology aimed at improving the concurrent error property of combinational TSC devices. The methodology is based on an iterative application of a structural modification of the device (observability modification) and an evaluation of the impact of such a modification. The quality evaluation is performed by means of a cost function for totally self-checking combinational devices which takes into account different aspects besides the area overhead criterion for comparing different realization strategies. The methodology has been validated on a set of MCNC91 benchmarks.