A methodology for designing systems with concurrent error detection capability is introduced. The proposed approach consists of a functional architecture and a checking architecture to verify data computed by the functional one. The methodology reduces both redundancy and latency through hardware resources and data sharing, respectively.
Concurrent error detection at architectural level
BOLCHINI, CRISTIANA;FORNACIARI, WILLIAM;SALICE, FABIO;SCIUTO, DONATELLA
1998-01-01
Abstract
A methodology for designing systems with concurrent error detection capability is introduced. The proposed approach consists of a functional architecture and a checking architecture to verify data computed by the functional one. The methodology reduces both redundancy and latency through hardware resources and data sharing, respectively.File in questo prodotto:
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