Designing ad-hoc codes for the realization of fault tolerant CMOS networks

An evolution of the already introduced technique for synthesis of CMOS gate structures tolerating all single transistor stuck-on faults and a large set of multiple faults is presented. Such technique is aimed at guaranteeing fault tolerance for a multiple output gate through the application of an AUED separated encoding of the output functions and the introduction of additional transistors, to avoid fault propagation. The improvement consists in the generation of an ad-hoc AUED code tailored on the circuit being designed, so that the number of additional transistors can be reduced.