This paper presents a methodology and framework to model the behavior of superscalar microprocessors. The simulation is focused on timing analysis and ignores all functional aspects. The methodology also provides a framework for building new simulators for generic architectures. The results obtained show a good accuracy and a satisfactory computational efficiency. Furthermore, the C++ SDK allows rapid development of new processor models making the methodology suitable for design space exploration over new processor architectures.

Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures

BRANDOLESE, CARLO;FORNACIARI, WILLIAM;SALICE, FABIO
2004-01-01

Abstract

This paper presents a methodology and framework to model the behavior of superscalar microprocessors. The simulation is focused on timing analysis and ignores all functional aspects. The methodology also provides a framework for building new simulators for generic architectures. The results obtained show a good accuracy and a satisfactory computational efficiency. Furthermore, the C++ SDK allows rapid development of new processor models making the methodology suitable for design space exploration over new processor architectures.
2004
PATMOS 2004: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
3540230955
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/266846
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