In many applications a software implementation of ECC (elliptic curve cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are needed. We present some results about a novel hardware implementation for ECC, that introduces also a form of parallelism to maximize the use of function units and hence to improve the throughput. Then we propose a comprehensive comparison of this new architecture with both some RSA architectures and other ECC implementations in ASIC VLSI technology.

A parallelized design for an elliptic curve cryptosystem coprocessor

BERTONI, GUIDO MARCO;BREVEGLIERI, LUCA ODDONE;SOZZANI, FRANCA;
2005-01-01

Abstract

In many applications a software implementation of ECC (elliptic curve cryptography) might be inappropriate due to performance requirements, therefore hardware implementations are needed. We present some results about a novel hardware implementation for ECC, that introduces also a form of parallelism to maximize the use of function units and hence to improve the throughput. Then we propose a comprehensive comparison of this new architecture with both some RSA architectures and other ECC implementations in ASIC VLSI technology.
2005
Proceedings of the IEEE Information Technology: Coding and Computing, 2005. ITCC 2005
0769523153
INF; cryptography; digital circuit; parallel architecture; elliptic curve
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/266821
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