This paper proposes a methodology for designing FPGAs able to self-detect the occurrence of hardware failures, integrated in a standard, industrial design flow. The approach improves the results proposed in the past, by defining a testing environment which takes into account the peculiarities of FPGA platforms.
An Integrated Approach for Designing Self-Checking FPGAs
BOLCHINI, CRISTIANA;SALICE, FABIO;SCIUTO, DONATELLA;
2003-01-01
Abstract
This paper proposes a methodology for designing FPGAs able to self-detect the occurrence of hardware failures, integrated in a standard, industrial design flow. The approach improves the results proposed in the past, by defining a testing environment which takes into account the peculiarities of FPGA platforms.File in questo prodotto:
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