The paper presents a solution to protect FSM implemented on FPGAs from SEU, exploiting the embedded memories available in modern FPGA devices and a Hamming code for error detection and correction. A fault tolerant FSM architecture is presented, along with a generator to automate the FSM implementation. Experimental results show that this solution is particularly suited especially when FSMs with a large number of outputs are present in the target design

RAM-based fault tolerant state machines for FPGAs

FRIGERIO, LAURA;SALICE, FABIO
2007-01-01

Abstract

The paper presents a solution to protect FSM implemented on FPGAs from SEU, exploiting the embedded memories available in modern FPGA devices and a Hamming code for error detection and correction. A fault tolerant FSM architecture is presented, along with a generator to automate the FSM implementation. Experimental results show that this solution is particularly suited especially when FSMs with a large number of outputs are present in the target design
2007
9780769528854
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/255832
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