This paper introduces a power estimation methodology operating at the instruction-level which is tightly related to the characteristics of the paralel system architecture, mainly in terms of one or more target processors, the memory sub-system, the system-level buses and the coprocessors.

Instruction-Level Power Estimation for Embedded VLIW Cores

SAMI, MARIAGIOVANNA;SCIUTO, DONATELLA;SILVANO, CRISTINA;ZACCARIA, VITTORIO
2000-01-01

Abstract

This paper introduces a power estimation methodology operating at the instruction-level which is tightly related to the characteristics of the paralel system architecture, mainly in terms of one or more target processors, the memory sub-system, the system-level buses and the coprocessors.
2000
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000
1581132689
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/245623
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