This paper extends the state of the art by improving the energy characterization efficiency of state-of-the-art ILP (instruction level parallelism) processors. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction.

Energy Estimation and Optimization of Embedded VLIW Processors based on Instruction Clustering

SAMI, MARIAGIOVANNA;SCIUTO, DONATELLA;SILVANO, CRISTINA;ZACCARIA, VITTORIO;
2002-01-01

Abstract

This paper extends the state of the art by improving the energy characterization efficiency of state-of-the-art ILP (instruction level parallelism) processors. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction.
2002
DAC '02 Proceedings of the 39th annual Design Automation Conference
1581134614
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11311/240457
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