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Fast Software-Level Power Estimation for Design Space Exploration 1-gen-2000 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
The design of Self-Checking Systems 1-gen-2000 BOLCHINI, CRISTIANASALICE, FABIO
Modeling the Effectiveness of Reuse in SoC Design 1-gen-2000 FORNACIARI, WILLIAMSALICE, FABIO
A Case Study in Design Space Exploration: The TOSCA Environment Applied to a Telecom Link Controller 1-gen-2000 ALLARA, ALBERTOFORNACIARI, WILLIAMSALICE, FABIO +
Energy Estimation for 32-Bit Microprocessors 1-gen-2000 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
A Multi-Level Strategy for Software Power Estimation 1-gen-2000 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
An Instruction-Level Functionality-Based Energy Estimation Model for 32-Bit Microprocessors 1-gen-2000 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
Design of VHDL based Totally Self-Checking Finite State machine and Data Path descriptions 1-gen-2000 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Reliability Properties Assessment at System Level: A Co-design Framework 1-gen-2001 BOLCHINI, CRISTIANAPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
Dynamic Modeling of Inter-Instruction Effects for Execution Time Estimation 1-gen-2001 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
Source-Level Execution Time Estimation of C Programs 1-gen-2001 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
Hw/Sw Co-simulation for fast design-space exploration of multiprocessor embedded systems 1-gen-2001 FORNACIARI, WILLIAMPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
Hardware-Software Timing Simulation Environment for Multiprocessor Embedded Systems 1-gen-2001 FORNACIARI, WILLIAMPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
Lambda-Block Analysis of VHDL for Design Reuse 1-gen-2001 FORNACIARI, WILLIAMSALICE, FABIO +
A Software Methodology for detecting Hardware Faults in VLIW Data Paths 1-gen-2001 BOLCHINI, CRISTIANAPOMANTE, LUIGISALICE, FABIO
On-Line Fault Detection in a Hardware/Software Co-design Environment 1-gen-2001 BOLCHINI, CRISTIANAPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
Development Cost and Size Estimation Starting from High-Level Specifications 1-gen-2001 FORNACIARI, WILLIAMSALICE, FABIO +
Designing Reliable Embedded Systems Based on 32 Bit Microprocessors 1-gen-2001 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
An Assembly-Level Execution-Time Model for Pipelined Architectures 1-gen-2001 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
Designing Self-Checking FPGAs Through Error Detection Codes 1-gen-2002 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA
Modeling Assembly Instruction Timing in Superscalar Architectures 1-gen-2002 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems 1-gen-2002 BOLCHINI, CRISTIANAPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
Metrics for Design Space Exploration of Heterogeneous Multiprocessor Embedded Systems 1-gen-2002 FORNACIARI, WILLIAMPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
Reliability Properties Assessment at System Level: A Co-design Framework 1-gen-2002 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
The impact of source code transformations on software power and energy consumption 1-gen-2002 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
Static power modeling of 32-bit microprocessors 1-gen-2002 BRANDOLESE, CARLOSALICE, FABIOFORNACIARI, WILLIAMSCIUTO, DONATELLA
Physical and Logical Data Structures for Very Small Databases 1-gen-2002 BOLCHINI, CRISTIANASALICE, FABIOSCHREIBER, FABIO ALBERTOTANCA, LETIZIA
Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures 1-gen-2003 FORNACIARI, WILLIAMPOMANTE, LUIGISALICE, FABIO +
A First Step Towards Hw/Sw Partitioning of UML Specifications 1-gen-2003 FORNACIARI, WILLIAMSALICE, FABIO +
Logical and Physical Design Issues for Smart Card Databases 1-gen-2003 BOLCHINI, CRISTIANASALICE, FABIOSCHREIBER, FABIO ALBERTOTANCA, LETIZIA
An Integrated Approach for Designing Self-Checking FPGAs 1-gen-2003 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Early Estimation of the Size of VHDL Projects 1-gen-2003 FORNACIARI, WILLIAMSALICE, FABIOSCARPAZZA, DANIELE PAOLO
An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System 1-gen-2003 FORNACIARI, WILLIAMPOMANTE, LUIGISALICE, FABIOSCIUTO, DONATELLA
The Design of Reliable Devices for Mission Critical Applications 1-gen-2003 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures 1-gen-2004 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIO
An Area Estimation Methodology for FPGA Based Designs at SystemC-Level 1-gen-2004 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIO
Reliable System Co-Design: the FIR Case Study 1-gen-2004 BOLCHINI, CRISTIANAMIELE, ANTONIO ROSARIOSALICE, FABIOSCIUTO, DONATELLA +
Source Level Models for Software Power Optimization 1-gen-2004 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIO
Analysis and Modeling of Energy Reducing Source Code Transformations 1-gen-2004 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA
A model of soft error effects in generic IP processors 1-gen-2005 BOLCHINI, CRISTIANAMIELE, ANTONIO ROSARIOSALICE, FABIOSCIUTO, DONATELLA
A SoC-Based Methodology for Cycle-Accurate RTOS System Call Timing Characterization 1-gen-2005 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIO
Toward an FPGA Implementation of XCS 1-gen-2005 BOLCHINI, CRISTIANAFERRANDI, PAOLO GIACOMOLANZI, PIER LUCASALICE, FABIO
Reliable System Specification for Self-Checking Data-Paths 1-gen-2005 BOLCHINI, CRISTIANASALICE, FABIOSCIUTO, DONATELLA +
Affinity-driven system design exploration for heterogeneous multiprocessor SoC 1-gen-2006 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIOSCIUTO, DONATELLA +
Evolving classifiers on field programmable gate arrays: Migrating XCS to FPGAs 1-gen-2006 BOLCHINI, CRISTIANAFERRANDI, PAOLO GIACOMOLANZI, PIER LUCASALICE, FABIO
DPM at OS level: low-power scheduling policies 1-gen-2006 BRANDOLESE, CARLOFORNACIARI, WILLIAMPOMANTE, LUIGISALICE, FABIO +
Energy aware scheduling of processes at OS level 1-gen-2006 BRANDOLESE, CARLOFORNACIARI, WILLIAMSALICE, FABIO +
A Data-Path Oriented, IP-Based Framework for flexible Design Exploration 1-gen-2006 BOLCHINI, CRISTIANABRANDOLESE, CARLOFORNACIARI, WILLIAMFRIGERIO, LAURASALICE, FABIO
Exploiting RAM for fault-tolerant functions in FPGA 1-gen-2007 FRIGERIO, LAURASALICE, FABIO
RAM-based fault tolerant state machines for FPGAs 1-gen-2007 FRIGERIO, LAURASALICE, FABIO
Mostrati risultati da 51 a 100 di 168
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