Sfoglia per Autore
Fast Software-Level Power Estimation for Design Space Exploration
2000-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio; Sciuto, Donatella
The design of Self-Checking Systems
2000-01-01 Bolchini, Cristiana; Salice, Fabio
Modeling the Effectiveness of Reuse in SoC Design
2000-01-01 Fornaciari, William; Salice, Fabio
A Case Study in Design Space Exploration: The TOSCA Environment Applied to a Telecom Link Controller
2000-01-01 Allara, Alberto; Fornaciari, William; B., Massimo; Salice, Fabio
Energy Estimation for 32-Bit Microprocessors
2000-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio; Sciuto, Donatella
A Multi-Level Strategy for Software Power Estimation
2000-01-01 Brandolese, Carlo; Fornaciari, William; L., Pomante; Salice, Fabio; Sciuto, Donatella
An Instruction-Level Functionality-Based Energy Estimation Model for 32-Bit Microprocessors
2000-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio; Sciuto, Donatella
Design of VHDL based Totally Self-Checking Finite State machine and Data Path descriptions
2000-01-01 Bolchini, Cristiana; R., Montandon; Salice, Fabio; Sciuto, Donatella
Reliability Properties Assessment at System Level: A Co-design Framework
2001-01-01 Bolchini, Cristiana; Pomante, Luigi; Salice, Fabio; Sciuto, Donatella
Dynamic Modeling of Inter-Instruction Effects for Execution Time Estimation
2001-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio; Sciuto, Donatella
Source-Level Execution Time Estimation of C Programs
2001-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio; Sciuto, Donatella
Hw/Sw Co-simulation for fast design-space exploration of multiprocessor embedded systems
2001-01-01 Fornaciari, William; Pomante, Luigi; Salice, Fabio; Sciuto, Donatella
Hardware-Software Timing Simulation Environment for Multiprocessor Embedded Systems
2001-01-01 Fornaciari, William; Pomante, Luigi; Salice, Fabio; Sciuto, Donatella
Lambda-Block Analysis of VHDL for Design Reuse
2001-01-01 Fornaciari, William; S., Minonne; Salice, Fabio; M., Vincenzi
A Software Methodology for detecting Hardware Faults in VLIW Data Paths
2001-01-01 Bolchini, Cristiana; Pomante, Luigi; Salice, Fabio
On-Line Fault Detection in a Hardware/Software Co-design Environment
2001-01-01 Bolchini, Cristiana; Pomante, Luigi; Salice, Fabio; Sciuto, Donatella
Development Cost and Size Estimation Starting from High-Level Specifications
2001-01-01 U., Bondi; Fornaciari, William; E., Magini; Salice, Fabio
Designing Reliable Embedded Systems Based on 32 Bit Microprocessors
2001-01-01 Bolchini, Cristiana; Salice, Fabio; Sciuto, Donatella
An Assembly-Level Execution-Time Model for Pipelined Architectures
2001-01-01 G., Beltrame; Brandolese, Carlo; Fornaciari, William; Salice, Fabio; Sciuto, Donatella; V., Trianni
Designing Self-Checking FPGAs Through Error Detection Codes
2002-01-01 Bolchini, Cristiana; Salice, Fabio; Sciuto, Donatella
Modeling Assembly Instruction Timing in Superscalar Architectures
2002-01-01 G., Beltrame; Brandolese, Carlo; Fornaciari, William; Salice, Fabio; Sciuto, Donatella; V., Trianni
A System Level Approach in Designing Dual-Duplex Fault Tolerant Embedded Systems
2002-01-01 Bolchini, Cristiana; Pomante, Luigi; Salice, Fabio; Sciuto, Donatella
Metrics for Design Space Exploration of Heterogeneous Multiprocessor Embedded Systems
2002-01-01 Fornaciari, William; Pomante, Luigi; Salice, Fabio; Sciuto, Donatella
Reliability Properties Assessment at System Level: A Co-design Framework
2002-01-01 Bolchini, Cristiana; L., Pomante; Salice, Fabio; Sciuto, Donatella
The impact of source code transformations on software power and energy consumption
2002-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio; Sciuto, Donatella
Static power modeling of 32-bit microprocessors
2002-01-01 Brandolese, Carlo; Salice, Fabio; Fornaciari, William; Sciuto, Donatella
Physical and Logical Data Structures for Very Small Databases
2002-01-01 Bolchini, Cristiana; Salice, Fabio; Schreiber, FABIO ALBERTO; Tanca, Letizia
Partitioning of Embedded Applications onto Heterogeneous Multiprocessor Architectures
2003-01-01 V., Del Bello; Fornaciari, William; Pomante, Luigi; Salice, Fabio
A First Step Towards Hw/Sw Partitioning of UML Specifications
2003-01-01 Fornaciari, William; P., Micheli; Salice, Fabio; L., Zampella
Logical and Physical Design Issues for Smart Card Databases
2003-01-01 Bolchini, Cristiana; Salice, Fabio; Schreiber, FABIO ALBERTO; Tanca, Letizia
An Integrated Approach for Designing Self-Checking FPGAs
2003-01-01 Bolchini, Cristiana; Salice, Fabio; Sciuto, Donatella; R., Zavaglia
Early Estimation of the Size of VHDL Projects
2003-01-01 Fornaciari, William; Salice, Fabio; Scarpazza, DANIELE PAOLO
An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System
2003-01-01 Fornaciari, William; Pomante, Luigi; Salice, Fabio; Sciuto, Donatella
The Design of Reliable Devices for Mission Critical Applications
2003-01-01 Bolchini, Cristiana; L., Pomante; Salice, Fabio; Sciuto, Donatella
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures
2004-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio
An Area Estimation Methodology for FPGA Based Designs at SystemC-Level
2004-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio
Reliable System Co-Design: the FIR Case Study
2004-01-01 Bolchini, Cristiana; Miele, ANTONIO ROSARIO; L., Pomante; Salice, Fabio; Sciuto, Donatella
Source Level Models for Software Power Optimization
2004-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio
Analysis and Modeling of Energy Reducing Source Code Transformations
2004-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio; Sciuto, Donatella
A model of soft error effects in generic IP processors
2005-01-01 Bolchini, Cristiana; Miele, ANTONIO ROSARIO; Salice, Fabio; Sciuto, Donatella
A SoC-Based Methodology for Cycle-Accurate RTOS System Call Timing Characterization
2005-01-01 Brandolese, Carlo; Fornaciari, William; Salice, Fabio
Toward an FPGA Implementation of XCS
2005-01-01 Bolchini, Cristiana; Ferrandi, PAOLO GIACOMO; Lanzi, PIER LUCA; Salice, Fabio
Reliable System Specification for Self-Checking Data-Paths
2005-01-01 Bolchini, Cristiana; L., Pomante; Salice, Fabio; Sciuto, Donatella
Affinity-driven system design exploration for heterogeneous multiprocessor SoC
2006-01-01 Brandolese, Carlo; Fornaciari, William; L., Pomante; Salice, Fabio; Sciuto, Donatella
Evolving classifiers on field programmable gate arrays: Migrating XCS to FPGAs
2006-01-01 Bolchini, Cristiana; Ferrandi, PAOLO GIACOMO; Lanzi, PIER LUCA; Salice, Fabio
DPM at OS level: low-power scheduling policies
2006-01-01 Brandolese, Carlo; Fornaciari, William; Pomante, Luigi; Salice, Fabio; R., Zafalon
Energy aware scheduling of processes at OS level
2006-01-01 Brandolese, Carlo; Fornaciari, William; L., Pomante; Salice, Fabio; R., Zafalon
A Data-Path Oriented, IP-Based Framework for flexible Design Exploration
2006-01-01 Bolchini, Cristiana; Brandolese, Carlo; Fornaciari, William; Frigerio, Laura; Salice, Fabio
Exploiting RAM for fault-tolerant functions in FPGA
2007-01-01 Frigerio, Laura; Salice, Fabio
RAM-based fault tolerant state machines for FPGAs
2007-01-01 Frigerio, Laura; Salice, Fabio
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