Sfoglia per Autore  

Opzioni
Mostrati risultati da 41 a 60 di 68
Titolo Data di pubblicazione Autori File
A computing platform and method for synchronize the prototype execution and simulation of hardware devices 1-gen-2020 Davide Zoniwilliam fornaciari
Una piattaforma informatica per prevenire attacchi ai canali laterali 1-gen-2020 Davide ZoniWilliam Fornaciari
Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials 1-gen-2020 Davide ZoniAndrea GalimbertiWilliam Fornaciari
Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography 1-gen-2020 Davide ZoniAndrea GalimbertiWilliam Fornaciari
VGM-Bench: FPU Benchmark suite for Computer Vision, Computer Graphics and Machine Learning applications 1-gen-2020 Luca CremonaWilliam FornaciariAndrea GalimbertiAndrea RomanoniDavide Zoni
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks 1-gen-2020 A. BarenghiW. FornaciariG. PelosiD. Zoni
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 1-gen-2020 Zoni, DavideCremona, LucaFornaciari, William
A COMPUTING PLATFORM AND METHOD FOR SYNCHRONIZE THE PROTOTYPE EXECUTION AND SIMULATION OF HARDWARE DEVICE 1-gen-2021 Fornaciari W.Zoni D.
A COMPUTING PLATFORM FOR PREVENTING SIDE CHANNEL ATTACKS 1-gen-2021 Fornaciari W.Zoni D.
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale 1-gen-2021 Giovanni AgostaDaniele CattaneoWilliam FornaciariAndrea GalimbertiGiuseppe MassariFederico ReghenzaniFederico TerraneoDavide ZoniCarlo Brandolese +
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 1-gen-2021 Luca CremonaWilliam FornaciariDavide Zoni
An FPU design template to optimize the accuracy-efficiency-area trade-off 1-gen-2021 Davide ZoniAndrea GalimbertiWilliam Fornaciari
Integrating Side Channel Security in the FPGA Hardware Design Flow 1-gen-2021 A. BarenghiW. FornaciariG. PelosiD. Zoni +
On the Effectiveness of True Random Number Generators Implemented on FPGAs 1-gen-2022 Galli, DavideGalimberti, AndreaFornaciari, WilliamZoni, Davide
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach 1-gen-2022 Agosta, GiovanniBrandolese, CarloCattaneo, DanieleFornaciari, WilliamGalimberti, AndreaMassari, GiuseppeReghenzani, FedericoTerraneo, FedericoZoni, Davide +
Design of side-channel resistant power monitors 1-gen-2022 Zoni, DavideCremona, LucaFornaciari, William
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators 1-gen-2022 Montanaro G.Galimberti A.Zoni D. +
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems 1-gen-2022 A. GalimbertiD. Zoni +
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators 1-gen-2022 Davide Zoni +
Cost-effective fixed-point hardware support for RISC-V embedded systems 1-gen-2022 D. ZoniA. Galimberti
Mostrati risultati da 41 a 60 di 68
Legenda icone

  •  file ad accesso aperto
  •  file disponibili sulla rete interna
  •  file disponibili agli utenti autorizzati
  •  file disponibili solo agli amministratori
  •  file sotto embargo
  •  nessun file disponibile