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Mostrati risultati da 1 a 50 di 175
Titolo Data di pubblicazione Autori File
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 1-gen-2022 Be' G.Bertulessi L.Ricci L.Scaletti L.Mercandelli M.Lacaita A. L.Levantino S.Samori C.Bonfanti A. +
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise 1-gen-2022 Bertulessi, LucaMercandelli, MarioSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
A Digital PLL with Multi-tap LMS-based Bandwidth Control 1-gen-2022 Bertulessi, LucaSamori, CarloLevantino, Salvatore +
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 1-gen-2022 Dartizio S. M.Buccoleri F.Tesolin F.Bertulessi L.Bevilacqua A.Samori C.Lacaita A. L.Levantino S. +
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 1-gen-2022 Buccoleri F.Dartizio S. M.Tesolin F.Santiccioli A.Bevilacqua A.Bertulessi L.Cherniak D.Samori C.Lacaita A. L.Levantino S. +
A Novel Topology of Coupled Phase-Locked Loops 1-gen-2021 Karman, SalehTesolin, FrancescoLevantino, SalvatoreSamori, Carlo
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 1-gen-2021 Mercandelli M.Santiccioli A.Dartizio S. M.Shehata A.Tesolin F.Karman S.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2021 Santiccioli A.Mercandelli M.Dartizio S. M.Tesolin F.Shehata A.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability 1-gen-2021 Karman S.Tesolin F.Dago A.Mercandelli M.Samori C.Levantino S.
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends 1-gen-2021 Karman S.Levantino S.Mazzanti A.Samori C.Tesolin F. +
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs 1-gen-2021 Mercandelli M.Levantino S.Samori C. +
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2021 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter 1-gen-2021 Mercandelli, MarioBertulessi, LucaSamori, CarloLevantino, Salvatore
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity 1-gen-2021 Angelo ParisiMario MercandelliCarlo SamoriAndrea Leonardo Lacaita
Digital PLLs: The modern timing reference for radar and communication systems 1-gen-2021 C. SamoriL. Bertulessi
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 1-gen-2021 Mercandelli, MarioSanticcioli, AlessioParisi, AngeloBertulessi, LucaLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
Jitter Minimization in Digital PLLs with Mid-Rise TDCs 1-gen-2020 Karman S.Samori C.Levantino S. +
Bang-bang digital PLLs for wireless systems 1-gen-2020 S. Levantinoc. Samori
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Mercandelli, MarioBertulessi, LucaParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 1-gen-2020 Mercandelli M.Santiccioli A.Parisi A.Bertulessi L.Lacaita A. L.Samori C.Levantino S. +
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 1-gen-2020 Mercandelli, MarioBertulessi, LucaSanticcioli, AlessioSamori, CarloLevantino, Salvatore +
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Santiccioli A.Mercandelli M.Bertulessi L.Parisi A.Lacaita A. L.Samori C.Levantino S. +
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 1-gen-2019 Grimaldi, LuigiBertulessi, LucaKarman, SalehSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power 1-gen-2019 Santiccioli, AlessioMercandelli, MarioLacaita, Andrea L.Samori, CarloLevantino, Salvatore
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper) 1-gen-2019 Cherniak D.Samori C.Levantino S.
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 1-gen-2019 Bertulessi, LucaKarman, SalehCherniak, DmytroGarghetti, AlessandroSamori, CarloLacaita, Andrea L.Levantino, Salvatore
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops 1-gen-2019 Santiccioli, AlessioSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power 1-gen-2019 Santiccioli A.Mercandelli M.Lacaita A. L.Samori C.Levantino S.
Low Power RF Digital PLLs with Direct Carrier Modulation 1-gen-2018 Salvatore LevantinoCarlo Samori
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 1-gen-2018 Bertulessi, LucaGrimaldi, LuigiCherniak, DmytroSamori, CarloLevantino, Salvatore
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 1-gen-2018 Cherniak, DmytroGrimaldi, LuigiBertulessi, LucaSamori, CarloLevantino, Salvatore +
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs 1-gen-2018 Vo, Tuan MinhSamori, CarloLevantino, Salvatore
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators 1-gen-2018 Cherniak, DmytroGrimaldi, LuigiSamori, CarloLevantino, Salvatore
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur 1-gen-2018 Cherniak, DmytroGRIMALDI, LUIGIBASSI, MATTEOSamori, CarloLevantino, Salvatore +
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 1-gen-2018 Cherniak, DmytroGrimaldi, LuigiBertulessi, LucaSamori, CarloLevantino, Salvatore +
Digitally-Assisted Frequency Synthesizers for Fast Chirp Generation in mm-Wave radars 1-gen-2018 S. LevantinoC. Samori
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 1-gen-2018 MERCANDELLI, MARIOLuigi GrimaldiLuca BertulessiCarlo SamoriAndrea L. LacaitaSalvatore Levantino
Impact of CMOS Scaling on Switched-Capacitor Power Amplifiers 1-gen-2018 TRUPPI, ALESSANDROSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique 1-gen-2017 Cherniak, DmytroSamori, CarloLevantino, Salvatore +
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars 1-gen-2017 CHERNIAK, DMYTROLEVANTINO, SALVATORESAMORI, CARLO +
Power-jitter trade-off analysis in digital-to-time converters 1-gen-2017 SANTICCIOLI, ALESSIOSAMORI, CARLOLACAITA, ANDREA LEONARDOLEVANTINO, SALVATORE
A novel segmentation scheme for DTC-based ΔΣ fractional-N PLL 1-gen-2017 VO, TUAN MINHSAMORI, CARLOLACAITA, ANDREA LEONARDOLEVANTINO, SALVATORE
Analysis of power efficiency in high-performance class-B oscillators 1-gen-2016 BERTULESSI, LUCALEVANTINO, SALVATORESAMORI, CARLO
Understanding Phase Noise in LC VCOs: A Key Problem in RF Integrated Circuits 1-gen-2016 SAMORI, CARLO
Wideband chirp generation techniques in digital phase-locked loops 1-gen-2016 CHERNIAK, DMYTROLEVANTINO, SALVATORESAMORI, CARLO +
Analysis of adaptive pre-distortion in DTC-based digital fractional-N PLLs 1-gen-2016 LEVANTINO, SALVATOREGRIMALDI, LUIGISAMORI, CARLO
Analysis of fractional-n bang-bang digital PLLs using phase switching technique 1-gen-2016 VO, TUAN MINHLEVANTINO, SALVATORESAMORI, CARLO
All-Digital Phase-Locked Loops for Linear Wideband Phase Modulation 1-gen-2015 LEVANTINO, SALVATORESAMORI, CARLO +
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop 1-gen-2015 LEVANTINO, SALVATORESAMORI, CARLOLACAITA, ANDREA LEONARDO +
Analysis and Design of Low-Jitter Digital Bang-Bang Phase-Locked Loops 1-gen-2014 MARUCCI, GIOVANNILEVANTINO, SALVATOREMAFFEZZONI, PAOLOSAMORI, CARLO
Mostrati risultati da 1 a 50 di 175
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