Sfoglia per Autore
A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk
In corso di stampa Ricci, Luca; Be', Gabriele; Rocco, Michele; Scaletti, Lorenzo; Zanoletti, Gabriele; Bertulessi, Luca; Lacaita, Andrea; Levantino, Salvatore; Samori, Carlo; Bonfanti, ANDREA GIOVANNI
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector
2024-01-01 Dartizio, S. M.; Rossoni, M.; Tesolin, F.; Castoro, G.; Samori, C.; Lacaita, A. L.; Levantino, S.
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique
2024-01-01 Moleri, Riccardo; Dartizio, Simone Mattia; Rossoni, Michele; Castoro, Giacomo; Tesolin, Francesco; Cherniak, Dmytro; Samori, Carlo; Lacaita, Andrea Leonardo; Levantino, Salvatore
A 250-MS/s 9.9-ENOB 80.7dB-SFDR Top-Plate Input SAR ADC with Charge Linearization
2024-01-01 Zanoletti, Gabriele; Scaletti, Lorenzo; Be', Gabriele; Ricci, Luca; Rocco, Michele; Bertulessi, Luca; Samori, Carlo; Bonfanti, Andrea
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and −252.4dB FoM
2024-01-01 Rossoni, Michele; Dartizio, Simone Mattia; Tesolin, Francesco; Castoro, Giacomo; Dell'Orto, Riccardo; Samori, Carlo; Lacaita, Andrea Leonardo; Levantino, Salvatore
A Highly Energy-Efficient FIA-based AZ-free Ring Amplifier for Pipeline-SAR ADCs
2024-01-01 Ceroni, A.; Zanoletti, G.; Bonfanti, A.; Samori, C.
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion
2024-01-01 Tesolin, Francesco; Dartizio, Simone Mattia; Castoro, Giacomo; Buccoleri, Francesco; Rossoni, Michele; Cherniak, Dmytro; Samori, Carlo; Lacaita, Andrea Leonardo; Levantino, Salvatore
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS
2023-01-01 Ricci, L.; Scaletti, L.; Be', G.; Rocco, M.; Bertulessi, L.; Levantino, S.; Lacaita, A.; Samori, C.; Bonfanti, A.
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
2023-01-01 Dartizio, Sm; Tesolin, F; Castoro, G; Buccoleri, F; Rossoni, M; Cherniak, D; Samori, C; Lacaita, Al; Levantino, S
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering
2023-01-01 Dartizio, Simone M.; Tesolin, Francesco; Castoro, Giacomo; Buccoleri, Francesco; Lanzoni, Luca; Rossoni, Michele; Cherniak, Dmytro; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology
2023-01-01 Castoro, Giacomo; Dartizio, Simone M.; Tesolin, Francesco; Buccoleri, Francesco; Rossoni, Michele; Cherniak, Dmytro; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner
2023-01-01 Buccoleri, F; Dartizio, Sm; Tesolin, F; Avallone, L; Santiccioli, A; Iesurum, A; Steffan, G; Cherniak, D; Bertulessi, L; Bevilacqua, A; Samori, C; Lacaita, Al; Levantino, S
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays
2023-01-01 Tesolin, Francesco; Dartizio, Simone M.; Buccoleri, Francesco; Santiccioli, Alessio; Bertulessi, Luca; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching
2022-01-01 Dartizio, S. M.; Buccoleri, F.; Tesolin, F.; Avallone, L.; Santiccioli, A.; Iesurum, A.; Steffan, G.; Cherniak, D.; Bertulessi, L.; Bevilacqua, A.; Samori, C.; Lacaita, A. L.; Levantino, S.
A Digital PLL with Multi-tap LMS-based Bandwidth Control
2022-01-01 Mercandelli, Mario; Bertulessi, Luca; Samori, Carlo; Levantino, Salvatore
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise
2022-01-01 Bertulessi, Luca; Cherniak, Dmytro; Mercandelli, Mario; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler
2022-01-01 Buccoleri, F.; Dartizio, S. M.; Tesolin, F.; Avallone, L.; Santiccioli, A.; Lesurum, A.; Steffan, G.; Bevilacqua, A.; Bertulessi, L.; Cherniak, D.; Samori, C.; Lacaita, A. L.; Levantino, S.
Concurrent effect of redundancy and switching algorithms in SAR ADCs
2022-01-01 Ricci, Luca; Scaletti, Lorenzo; Be', Gabriele; Bertulessi, Luca; Levantino, Salvatore; Samori, Carlo; Bonfanti, Andrea
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations
2022-01-01 Be', G.; Parisi, A.; Bertulessi, L.; Ricci, L.; Scaletti, L.; Mercandelli, M.; Lacaita, A. L.; Levantino, S.; Samori, C.; Bonfanti, A.
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter
2022-01-01 Mercandelli, Mario; Santiccioli, Alessio; Parisi, Angelo; Bertulessi, Luca; Cherniak, Dmytro; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters
2022-01-01 Scaletti, Lorenzo; Be', Gabriele; Parisi, Angelo; Bertulessi, Luca; Ricci, Luca; Mercandelli, Mario; Levantino, Salvatore; Samori, Carlo; Bonfanti, ANDREA GIOVANNI
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping
2022-01-01 Dartizio, Simone M.; Tesolin, Francesco; Mercandelli, Mario; Santiccioli, Alessio; Shehata, Abanob; Karman, Saleh; Bertulessi, Luca; Buccoleri, Francesco; Avallone, Luca; Parisi, Angelo; Lacaita, Andrea L.; Kennedy, Michael P.; Samori, Carlo; Levantino, Salvatore
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time
2022-01-01 Dartizio, Simone M.; Buccoleri, Francesco; Tesolin, Francesco; Avallone, Luca; Santiccioli, Alessio; Iesurum, Agata; Steffan, Giovanni; Cherniak, Dmytro; Bertulessi, Luca; Bevilacqua, Andrea; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter
2021-01-01 Mercandelli, Mario; Bertulessi, Luca; Samori, Carlo; Levantino, Salvatore
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs
2021-01-01 Avallone, L.; Mercandelli, M.; Santiccioli, A.; Kennedy, M. P.; Levantino, S.; Samori, C.
A 18.9-22.3GHz Dual-Core Digital PLL with On-Chip Power Combination for Phase Noise and Power Scalability
2021-01-01 Karman, S.; Tesolin, F.; Dago, A.; Mercandelli, M.; Samori, C.; Levantino, S.
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays
2021-01-01 Santiccioli, A.; Mercandelli, M.; Dartizio, S. M.; Tesolin, F.; Karman, S.; Shehata, A.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Cherniak, D.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S.
Digital PLLs: The modern timing reference for radar and communication systems
2021-01-01 Samori, C.; Bertulessi, L.
A Novel Topology of Coupled Phase-Locked Loops
2021-01-01 Karman, Saleh; Tesolin, Francesco; Levantino, Salvatore; Samori, Carlo
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter
2021-01-01 Mercandelli, M.; Santiccioli, A.; Dartizio, S. M.; Shehata, A.; Tesolin, F.; Karman, S.; Bertulessi, L.; Buccoleri, F.; Avallone, L.; Parisi, A.; Lacaita, A. L.; Kennedy, M. P.; Samori, C.; Levantino, S.
A PLL-Based Digital Technique for Orthogonal Correction of ADC Non-Linearity
2021-01-01 Parisi, Angelo; Mercandelli, Mario; Samori, Carlo; Lacaita, ANDREA LEONARDO
SiGe BiCMOS Building Blocks for E- and D-Band Backhauling Front-Ends
2021-01-01 Amendola, G.; Boccia, L.; Centurelli, F.; Chevalier, P.; Fonte, A.; Karman, S.; Levantino, S.; Mazzanti, A.; Mustacchio, C.; Pallotta, A.; Petricli, I.; Samori, C.; Tesolin, F.; Tommasino, P.; Traversa, A.; Trifiletti, A.
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
2020-01-01 Mercandelli, M.; Santiccioli, A.; Parisi, A.; Bertulessi, L.; Cherniak, D.; Lacaita, A. L.; Samori, C.; Levantino, S.
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking
2020-01-01 Santiccioli, Alessio; Mercandelli, Mario; Bertulessi, Luca; Parisi, Angelo; Cherniak, Dmytro; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL
2020-01-01 Cherniak, Dmytro; Mercandelli, Mario; Bertulessi, Luca; Padovan, Fabio; Grimaldi, Luigi; Santiccioli, Alessio; Aichner, Michael; Samori, Carlo; Levantino, Salvatore
Jitter Minimization in Digital PLLs with Mid-Rise TDCs
2020-01-01 Avallone, L.; Kennedy, M. P.; Karman, S.; Samori, C.; Levantino, S.
Bang-bang digital PLLs for wireless systems
2020-01-01 Levantino, S.; Samori, C.
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking
2020-01-01 Santiccioli, A.; Mercandelli, M.; Bertulessi, L.; Parisi, A.; Cherniak, D.; Lacaita, A. L.; Samori, C.; Levantino, S.
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper)
2019-01-01 Cherniak, D.; Samori, C.; Levantino, S.
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power
2019-01-01 Santiccioli, A.; Mercandelli, M.; Lacaita, A. L.; Samori, C.; Levantino, S.
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS
2019-01-01 Bertulessi, Luca; Karman, Saleh; Cherniak, Dmytro; Garghetti, Alessandro; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS
2019-01-01 Grimaldi, Luigi; Bertulessi, Luca; Karman, Saleh; Cherniak, Dmytro; Garghetti, Alessandro; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops
2019-01-01 Santiccioli, Alessio; Samori, Carlo; Lacaita, Andrea L.; Levantino, Salvatore
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power
2019-01-01 Santiccioli, Alessio; Mercandelli, Mario; Lacaita, Andrea L.; Samori, Carlo; Levantino, Salvatore
Low Power RF Digital PLLs with Direct Carrier Modulation
2018-01-01 Levantino, Salvatore; Samori, Carlo
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur
2018-01-01 Cherniak, Dmytro; Grimaldi, Luigi; Padovan, Fabio; Bassi, Matteo; Nonis, Roberto; Samori, Carlo; Levantino, Salvatore
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators
2018-01-01 Cherniak, Dmytro; Grimaldi, Luigi; Samori, Carlo; Levantino, Salvatore
A Novel LMS-Based Calibration Scheme for Fractional-N Digital PLLs
2018-01-01 Vo, TUAN MINH; Samori, Carlo; Levantino, Salvatore
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation
2018-01-01 Cherniak, Dmytro; Grimaldi, Luigi; Bertulessi, Luca; Samori, Carlo; Nonis, Roberto; Levantino, Salvatore
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range
2018-01-01 Bertulessi, Luca; Grimaldi, Luigi; Cherniak, Dmytro; Samori, Carlo; Levantino, Salvatore
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