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Mostrati risultati da 1 a 50 di 195
Titolo Data di pubblicazione Autori File
A Wide-Input-Range Time-Based Buck Converter With Adaptive Gain and Continuous Phase Preset for Seamless PFM/PWM Transitions 1-gen-2024 Melillo, PaoloZaffin, SimoneLeoncini, MauroLevantino, SalvatoreGhioni, Massimo +
Insights on the Dynamic Performance of Nonminimum-Phase Boost Converters Exploiting Inductor-Current-Feedback RHPZ Mitigation 1-gen-2024 Melillo, PaoloLeoncini, MauroLevantino, SalvatoreGhioni, Massimo
A 1-A 90% Peak Efficiency 5–36-V Input Voltage Time-Based Buck Converter with Adaptive Gain Compensation and Controlled-Skip Operation 1-gen-2024 Leoncini, MauroMelillo, PaoloLevantino, SalvatoreGhioni, Massimo +
METHOD FOR CONTROLLING A SINGLE INPUT DUAL OUTPUT DC-DC CONVERTER, CORRESPONDING CONVERTER AND COMPUTER PROGRAM PRODUCT 1-gen-2023 Leoncini M.Ghioni M.Levantino S. +
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2023 Tesolin, FrancescoDartizio, Simone M.Buccoleri, FrancescoSanticcioli, AlessioBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
Time-Based Buck Converter with Variable Frequency DCM and ON-Time Correction for Seamless Transitions 1-gen-2023 Melillo, PaoloZaffin, SimoneLevantino, SalvatoreGhioni, Massimo +
A Compact Wide-Input-Range Time-Domain Buck Converter with Fast Transient Response for Industrial Applications 1-gen-2023 Melillo, PaoloLeoncini, MauroZaffin, SimoneLevantino, SalvatoreGhioni, Massimo +
Integration of loop gain measurement circuit for stability evaluation in DC/DC converters with time-based control 1-gen-2023 Leoncini M.Melillo P.Levantino S.Ghioni M. +
High Power Density 4:1 Resonant Switched-Capacitor DC-DC Converter for PoL Applications 1-gen-2023 Dago, AlessandroLeoncini, MauroLevantino, SalvatoreGhioni, Massimo +
A High Power Density Quasi-Resonant Switched-Capacitor DC-DC Converter with Single Semi-Period Tank Current Modulation 1-gen-2023 Alessandro DagoMauro LeonciniSalvatore LevantinoMassimo Ghioni +
A Compact High-Efficiency Boost Converter With Time-Based Control, RHP Zero-Elimination, and Tracking Error Compensation 1-gen-2023 Leoncini, MauroDago, AlessandroLevantino, SalvatoreGhioni, Massimo +
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 1-gen-2023 Buccoleri, FDartizio, SMTesolin, FSanticcioli, ACherniak, DBertulessi, LBevilacqua, ASamori, CLacaita, ALLevantino, S +
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, Simone M.Tesolin, FrancescoCastoro, GiacomoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
Spread-Spectrum Frequency Modulation in a DC/DC Converter With Time-Based Control 1-gen-2023 Leoncini, MauroMelillo, PaoloLevantino, SalvatoreGhioni, Massimo +
A 2GS/s 11b 8x Interleaved ADC with 9.2 ENOB and 69.9dB SFDR in 28nm CMOS 1-gen-2023 L. RicciL. ScalettiG. Be'M. RoccoL. BertulessiS. LevantinoA. LacaitaC. SamoriA. Bonfanti
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 1-gen-2023 Castoro, GiacomoDartizio, Simone M.Tesolin, FrancescoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
Phase Noise Analysis of Periodically ON/OFF Switched Oscillators 1-gen-2023 Giacomo CastoroSimone M. DartizioAndrea L. LacaitaSalvatore Levantino
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, SMTesolin, FCastoro, GBuccoleri, FRossoni, MCherniak, DSamori, CLacaita, ALLevantino, S
DC-DC CONVERTER APPARATUS WITH TIME-BASED CONTROL LOOP AND CORRESPONDING CONTROL METHOD, AND COMPUTER PROGRAM PRODUCT 1-gen-2022 M. LeonciniM. GhioniS. Levantino +
Circuito convertitore DC-DC e corrispondente procedimento di funzionamento 1-gen-2022 Ghioni M.Levantino S.Melillo P. +
RHPZ Mitigation Technique for DC-DC Non-minimum Phase Converter Operating in CCM 1-gen-2022 S. LevantinoM. A. GhioniP. Melillo +
A Novel Feedforward Technique for Improved Line Transient in Time-Based-Controlled Boost Converters 1-gen-2022 Melillo, PaoloDago, AlessandroLevantino, SalvatoreGhioni, Massimo +
Recent Advances in High-Performance Frequency Synthesizer Design 1-gen-2022 Levantino S.
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise 1-gen-2022 Bertulessi, LucaMercandelli, MarioSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
Special Section on the 47th IEEE European Solid-State Circuits Conference (ESSCIRC) 1-gen-2022 Levantino S. +
A Novel Common-Gate Comparator with Auto-Zeroing Offset Cancellation 1-gen-2022 Dago, AlessandroLeoncini, MauroLevantino, SalvatoreGhioni, Massimo +
A 10.2-ENOB, 150-MS/s redundant SAR ADC with a quasi-monotonic switching algorithm for time-interleaved converters 1-gen-2022 Lorenzo ScalettiGabriele BeAngelo ParisiLuca BertulessiLuca RicciMario MercandelliSalvatore LevantinoCarlo SamoriAndrea Bonfanti
A 68.6fs_rms-Total-integrated-Jitter and 1.5us-Locking-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching 1-gen-2022 Dartizio S. M.Buccoleri F.Tesolin F.Bertulessi L.Bevilacqua A.Samori C.Lacaita A. L.Levantino S. +
A 900-MS/s SAR-based Time-Interleaved ADC with a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations 1-gen-2022 Be' G.Bertulessi L.Ricci L.Scaletti L.Mercandelli M.Lacaita A. L.Levantino S.Samori C.Bonfanti A. +
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping 1-gen-2022 Dartizio, Simone M.Tesolin, FrancescoMercandelli, MarioSanticcioli, AlessioShehata, AbanobKarman, SalehBertulessi, LucaBuccoleri, FrancescoParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
Analysis and Design of 8-to-101.6-GHz Injection-Locked Frequency Divider by Five With Concurrent Dual-Path Multi-Injection Topology 1-gen-2022 Garghetti A.Lacaita A. L.Levantino S. +
Frequency Synthesizers for 5G Applications 1-gen-2022 Levantino, Salvatore
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter 1-gen-2022 Mercandelli, MarioSanticcioli, AlessioParisi, AngeloBertulessi, LucaLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 1-gen-2022 Buccoleri F.Dartizio S. M.Tesolin F.Santiccioli A.Bevilacqua A.Bertulessi L.Cherniak D.Samori C.Lacaita A. L.Levantino S. +
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 1-gen-2022 Simone M. DartizioFrancesco BuccoleriFrancesco TesolinAlessio SanticcioliDmytro CherniakLuca BertulessiAndrea BevilacquaCarlo SamoriAndrea L. LacaitaSalvatore Levantino +
A Digital PLL with Multi-tap LMS-based Bandwidth Control 1-gen-2022 Bertulessi, LucaSamori, CarloLevantino, Salvatore +
Hybrid Resonant Switched-Capacitor Converter for 48 V to 3.4 V Direct Conversion 1-gen-2022 Dago, AlessandroLeoncini, MauroLevantino, SalvatoreGhioni, Massimo +
Concurrent effect of redundancy and switching algorithms in SAR ADCs 1-gen-2022 Ricci, LucaScaletti, LorenzoBe, GabrieleBertulessi, LucaLevantino, SalvatoreSamori, CarloBonfanti, Andrea
Integrated Loop-Gain Measurement Circuit for DC/DC Boost Converters with Time-Based Control 1-gen-2022 Leoncini, MauroMelillo, PaoloLevantino, SalvatoreGhioni, Massimo +
Convertitore DC-DC con anello di controllo basato sul tempo e corrispondente procedimento 1-gen-2021 M. GHIONIS. LEVANTINOM. LEONCINI +
PROCEDIMENTO PER IL CONTROLLO DI UN CONVERTITORE DC-DC SINGLE INPUT DUAL OUTPUT, CORRISPONDENTE CONVERTITORE E PRODOTTO INFORMATICO 1-gen-2021 M. GHIONIS. LEVANTINOM. LEONCINI +
CONVERTITORE SWITCHED-CAPACITOR, PROCEDIMENTO, SISTEMA DI ALIMENTAZIONE E DISPOSITIVO ELETTRONICO CORRISPONDENTI 1-gen-2021 A. DAGOS. LEVANTINOM. A. GHIONI +
Low-Phase-Noise PLL via Reference Path Coupling 1-gen-2021 CHERNIAK D.Levantino S.Santiccioli A.
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter 1-gen-2021 Mercandelli, MarioBertulessi, LucaSamori, CarloLevantino, Salvatore
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 1-gen-2021 Mercandelli M.Santiccioli A.Dartizio S. M.Shehata A.Tesolin F.Karman S.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A Novel Topology of Coupled Phase-Locked Loops 1-gen-2021 Karman, SalehTesolin, FrancescoLevantino, SalvatoreSamori, Carlo
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs 1-gen-2021 Mercandelli M.Levantino S.Samori C. +
A 13.6-69.1GHz 5.6mW Ring-Type Injection-Locked Frequency Divider by Five with >20% Continuous Locking Range and Operation up to 101.6GHz in 28nm CMOS 1-gen-2021 Andrea Leonardo LacaitaSalvatore Levantino +
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2021 Santiccioli A.Mercandelli M.Dartizio S. M.Tesolin F.Shehata A.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
An 800-mA Time-Based Boost Converter in 0.18um BCD with Right-Half-Plane Zero Elimination and 96% Power Efficiency 1-gen-2021 Leoncini M.Levantino S.Ghioni M. +
Mostrati risultati da 1 a 50 di 195
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