RE.PUBLIC@POLIMI pubblicazioni di ricerca del Politecnico di Milano

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A Deep Learning-assisted Template Attack Against Dynamic Frequency Scaling Countermeasures 1-gen-2024 Galli, DavideLattari, FrancescoMatteucci, MatteoZoni, Davide
A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS 1-gen-2024 Montanaro, GabrieleGalimberti, AndreaZoni, Davide
A Deep-Learning Technique to Locate Cryptographic Operations in Side-Channel Traces 1-gen-2024 Chiari, GiuseppeGalli, DavideLattari, FrancescoMatteucci, MatteoZoni, Davide
Blink: Fast Automated Design of Run-Time Power Monitors on FPGA-Based Computing Platforms 1-gen-2024 Galimberti, AndreaPiccoli, MicheleZoni, Davide
Design-time methodology for optimizing mixed-precision CPU architectures on FPGA 1-gen-2024 Denisov, LevGalimberti, AndreaCattaneo, DanieleAgosta, GiovanniZoni, Davide
Hound: Locating Cryptographic Primitives in Desynchronized Side-Channel Traces using Deep-Learning 1-gen-2024 Galli, DavideChiari, GiuseppeZoni, Davide
Functional ISS-Driven Verification of Superscalar RISC-V Processors 1-gen-2024 Galimberti, AndreaZoni, Davide +
ML-Assisted Attack Detection on NoC-Based Many-Cores Through On-Chip Traffic Monitoring 1-gen-2024 Galimberti, AndreaZoni, DavideFornaciari, William +
Rethinking the Switch Architecture for Stateful In-network Computing 1-gen-2024 Zoni D.Antichi G. +
The TEXTAROSSA Project: Cool all the Way Down to the Hardware 1-gen-2024 Agosta, GiovanniCattaneo, DanieleFornaciari, WilliamGalimberti, AndreaLeva, AlbertoReghenzani, FedericoLodi, Carlo SaverioTerraneo, FedericoZoni, Davide +
The Impact of Run-Time Variability on Side-Channel Attacks Targeting FPGAs 1-gen-2024 Galli, DavideGuarisco, AdrianoFornaciari, WilliamMatteucci, MatteoZoni, Davide
Dynamic Power Consumption of the Full Posit Processing Unit: Analysis and Experiments 1-gen-2023 Michele PiccoliDavide ZoniWilliam FornaciariGiueppe Massari +
An Evaluation of the State-Of-The-Art Software and Hardware Implementations of BIKE 1-gen-2023 Andrea GalimbertiGabriele MontanaroWilliam FornaciariDavide Zoni
RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 1-gen-2023 Fornaciari, WilliamReghenzani, FedericoAgosta, GiovanniZoni, DavideGalimberti, Andrea +
Hardware and Software Support for Mixed Precision Computing: A Roadmap for Embedded and HPC Systems 1-gen-2023 Fornaciari W.Agosta G.Cattaneo D.Denisov L.Galimberti A.Magnani G.Zoni D.
HLS-based acceleration of the BIKE post-quantum KEM on embedded-class heterogeneous SoCs 1-gen-2023 Galimberti, AndreaMontanaro, GabrieleZoni, Davide
A survey on run-time power monitors at the edge 1-gen-2023 Davide ZoniAndrea GalimbertiWilliam Fornaciari
FPGA implementation of BIKE for quantum-resistant TLS 1-gen-2022 Galimberti, AndreaGalli, DavideMontanaro, GabrieleFornaciari, WilliamZoni, Davide
On the Effectiveness of True Random Number Generators Implemented on FPGAs 1-gen-2022 Galli, DavideGalimberti, AndreaFornaciari, WilliamZoni, Davide
Design of side-channel resistant power monitors 1-gen-2022 Zoni, DavideCremona, LucaFornaciari, William
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach 1-gen-2022 Agosta, GiovanniBrandolese, CarloCattaneo, DanieleFornaciari, WilliamGalimberti, AndreaMassari, GiuseppeReghenzani, FedericoTerraneo, FedericoZoni, Davide +
On the use of hardware accelerators in QC-MDPC code-based cryptography 1-gen-2022 Galimberti, AndreaGalli, DavideMontanaro, GabrieleFornaciari, WilliamZoni, Davide
Efficient and scalable FPGA design of GF(2m) inversion for post-quantum cryptosystems 1-gen-2022 A. GalimbertiD. Zoni +
Gated-CNN: Combating NBTI and HCI aging effects in on-chip activation memories of Convolutional Neural Network accelerators 1-gen-2022 Davide Zoni +
Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators 1-gen-2022 Montanaro G.Galimberti A.Zoni D. +
Cost-effective fixed-point hardware support for RISC-V embedded systems 1-gen-2022 D. ZoniA. Galimberti
A COMPUTING PLATFORM AND METHOD FOR SYNCHRONIZE THE PROTOTYPE EXECUTION AND SIMULATION OF HARDWARE DEVICE 1-gen-2021 Fornaciari W.Zoni D.
Integrating Side Channel Security in the FPGA Hardware Design Flow 1-gen-2021 A. BarenghiW. FornaciariG. PelosiD. Zoni +
An FPU design template to optimize the accuracy-efficiency-area trade-off 1-gen-2021 Davide ZoniAndrea GalimbertiWilliam Fornaciari
TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale 1-gen-2021 Giovanni AgostaDaniele CattaneoWilliam FornaciariAndrea GalimbertiGiuseppe MassariFederico ReghenzaniFederico TerraneoDavide ZoniCarlo Brandolese +
Automatic identification and hardware implementation of a resource-constrained power model for embedded systems 1-gen-2021 Luca CremonaWilliam FornaciariDavide Zoni
A COMPUTING PLATFORM FOR PREVENTING SIDE CHANNEL ATTACKS 1-gen-2021 Fornaciari W.Zoni D.
A computing platform and method for synchronize the prototype execution and simulation of hardware devices 1-gen-2020 Davide Zoniwilliam fornaciari
Flexible and scalable FPGA-oriented design of multipliers for large binary polynomials 1-gen-2020 Davide ZoniAndrea GalimbertiWilliam Fornaciari
Efficient and scalable FPGA-oriented design of QC-LDPC bit-flipping decoders for post-quantum cryptography 1-gen-2020 Davide ZoniAndrea GalimbertiWilliam Fornaciari
VGM-Bench: FPU Benchmark suite for Computer Vision, Computer Graphics and Machine Learning applications 1-gen-2020 Luca CremonaWilliam FornaciariAndrea GalimbertiAndrea RomanoniDavide Zoni
Una piattaforma informatica per prevenire attacchi ai canali laterali 1-gen-2020 Davide ZoniWilliam Fornaciari
Scramble Suit: A Profile Differentiation Countermeasure to Prevent Template Attacks 1-gen-2020 A. BarenghiW. FornaciariG. PelosiD. Zoni
All-digital control-theoretic scheme to optimize energy budget and allocation in multi-cores 1-gen-2020 Zoni, DavideCremona, LucaFornaciari, William
A Fresh View on the Microarchitectural Design of FPGA-Based RISC CPUs in the IoT Era 1-gen-2019 Davide Zoni +
Evaluating the Trade-offs in the Hardware Design of the LEDAcrypt Encryption Functions 1-gen-2019 A. BarenghiW. FornaciariA. GalimbertiG. PelosiD. Zoni
Monitor and Knob Techniques in Network-on-Chip Architectures 1-gen-2019 Davide ZoniCANIDIO, ANDREAWilliam Fornaciari +
All-digital energy-constrained controller for general-purpose accelerators and CPUs 1-gen-2019 Davide ZoniLuca CremonaWilliam Fornaciari
Partial Packet Forwarding to Improve Performance in Fully Adaptive Routing for Cache-coherent NoCs 1-gen-2019 William FornaciariDavide Zoni +
Analysis and countermeasures to side-channel attacks: a hardware design perspective 1-gen-2019 davide zoni
DarkCache: Energy-performance Optimization of Tiled Multi-cores by Adaptively Power Gating LLC Banks 1-gen-2018 Davide ZoniWilliam Fornaciari +
PowerProbe: Run-time Power Modeling Through Automatic RTL Instrumentation 1-gen-2018 Davide ZoniLuca CremonaWilliam Fornaciari
Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems 1-gen-2018 Fornaciari, WilliamLibutti, SimoneMassari, GiuseppePupykina, AnnaReghenzani, FedericoZanella, MicheleAgosta, GiovanniZoni, DavideBrandolese, CarloCremona, LucaCilardo, Alessandro +
A Comprehensive Side-Channel Information Leakage Analysis of an In-Order RISC CPU Microarchitecture 1-gen-2018 D. ZoniA. BarenghiG. PelosiW. Fornaciari
Fast Estimations of Failure Probability Over Long Time Spans 1-gen-2018 Zoni, Davide +
Mostrati risultati da 1 a 50 di 80
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