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Mostrati risultati da 1 a 20 di 39
Titolo Data di pubblicazione Autori File
Analysis of power efficiency in high-performance class-B oscillators 1-gen-2016 BERTULESSI, LUCALEVANTINO, SALVATORESAMORI, CARLO
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 1-gen-2018 Cherniak, DmytroGrimaldi, LuigiBertulessi, LucaSamori, CarloLevantino, Salvatore +
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 1-gen-2018 Cherniak, DmytroGrimaldi, LuigiBertulessi, LucaSamori, CarloLevantino, Salvatore +
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 1-gen-2018 Bertulessi, LucaGrimaldi, LuigiCherniak, DmytroSamori, CarloLevantino, Salvatore
A Background Calibration Technique to Control the Bandwidth of Digital PLLs 1-gen-2018 MERCANDELLI, MARIOLuigi GrimaldiLuca BertulessiCarlo SamoriAndrea L. LacaitaSalvatore Levantino
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 1-gen-2019 Bertulessi, LucaKarman, SalehCherniak, DmytroGarghetti, AlessandroSamori, CarloLacaita, Andrea L.Levantino, Salvatore
16.7 A 30GHz Digital Sub-Sampling Fractional-N PLL with 198fs rms Jitter in 65nm LP CMOS 1-gen-2019 Grimaldi, LuigiBertulessi, LucaKarman, SalehSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Santiccioli A.Mercandelli M.Bertulessi L.Parisi A.Lacaita A. L.Samori C.Levantino S. +
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter 1-gen-2020 Mercandelli M.Santiccioli A.Parisi A.Bertulessi L.Lacaita A. L.Samori C.Levantino S. +
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking 1-gen-2020 Mercandelli, MarioBertulessi, LucaParisi, AngeloLacaita, Andrea L.Samori, CarloLevantino, Salvatore +
A 250Mb/s Direct Phase Modulator with -42.4dB EVM Based on a 14GHz Digital PLL 1-gen-2020 Mercandelli, MarioBertulessi, LucaSanticcioli, AlessioSamori, CarloLevantino, Salvatore +
A Timing Skew Correction Technique in Time-Interleaved ADCs Based on a DeltaSigma Digital-to-Time Converter 1-gen-2021 G. Be'M. MercandelliL. Bertulessi
A low-noise high-speed comparator for a 12-bit 200-MSps SAR ADC in a 28-nm CMOS process 1-gen-2021 L. RicciL. BertulessiA. Bonfanti
Digital PLLs: The modern timing reference for radar and communication systems 1-gen-2021 C. SamoriL. Bertulessi
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter 1-gen-2021 Mercandelli, MarioBertulessi, LucaSamori, CarloLevantino, Salvatore
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays 1-gen-2021 Santiccioli A.Mercandelli M.Dartizio S. M.Tesolin F.Shehata A.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
Frequency Synthesizers Based on Fast-Locking Bang-Bang PLL for Cellular Applications 1-gen-2021 Luca Bertulessi
Skew and Jitter Performance in CMOS Clock Phase Splitter Circuits 1-gen-2021 L. ScalettiA. ParisiL. Bertulessi
Self-Biasing Dynamic Start-up Circuit for Current-Biased Class-C Oscillators 1-gen-2021 Parisi, A.Tesolin, F.Mercandelli, M.Bertulessi, L.Lacaita, A. L.
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter 1-gen-2021 Mercandelli M.Santiccioli A.Dartizio S. M.Shehata A.Tesolin F.Karman S.Bertulessi L.Buccoleri F.Parisi A.Lacaita A. L.Samori C.Levantino S. +
Mostrati risultati da 1 a 20 di 39
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