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Titolo Data di pubblicazione Autori File
Wideband chirp generation techniques in digital phase-locked loops 1-gen-2016 CHERNIAK, DMYTROLEVANTINO, SALVATORESAMORI, CARLO +
Digital frequency synthesizer with robust injection locked divider 1-gen-2017 Dmytro CherniakSalvatore Levantino +
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique 1-gen-2017 Cherniak, DmytroSamori, CarloLevantino, Salvatore +
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars 1-gen-2017 CHERNIAK, DMYTROLEVANTINO, SALVATORESAMORI, CARLO +
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation 1-gen-2018 Cherniak, DmytroGrimaldi, LuigiBertulessi, LucaSamori, CarloLevantino, Salvatore +
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range 1-gen-2018 Bertulessi, LucaGrimaldi, LuigiCherniak, DmytroSamori, CarloLevantino, Salvatore
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation 1-gen-2018 Cherniak, DmytroGrimaldi, LuigiBertulessi, LucaSamori, CarloLevantino, Salvatore +
A 15.6-18.2 GHz digital bang-bang PLL with -63dBc in-band fractional spur 1-gen-2018 Cherniak, DmytroGRIMALDI, LUIGIBASSI, MATTEOSamori, CarloLevantino, Salvatore +
Adaptive Digital Pre-Emphasis for PLL-Based FMCW Modulators 1-gen-2018 Cherniak, DmytroGrimaldi, LuigiSamori, CarloLevantino, Salvatore
A 30-GHz Digital Sub-Sampling Fractional-N PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS 1-gen-2019 Bertulessi, LucaKarman, SalehCherniak, DmytroGarghetti, AlessandroSamori, CarloLacaita, Andrea L.Levantino, Salvatore
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS: (Invited Paper) 1-gen-2019 Cherniak D.Samori C.Levantino S.
Chirp Generators for Millimeter-Wave FMCW Radars 1-gen-2020 Cherniak D.Levantino S.
Low-Phase-Noise PLL via Reference Path Coupling 1-gen-2021 CHERNIAK D.Levantino S.Santiccioli A.
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler 1-gen-2022 Buccoleri F.Dartizio S. M.Tesolin F.Santiccioli A.Bevilacqua A.Bertulessi L.Cherniak D.Samori C.Lacaita A. L.Levantino S. +
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time 1-gen-2022 Simone M. DartizioFrancesco BuccoleriFrancesco TesolinAlessio SanticcioliDmytro CherniakLuca BertulessiAndrea BevilacquaCarlo SamoriAndrea L. LacaitaSalvatore Levantino +
4.5 A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology 1-gen-2023 Castoro, GiacomoDartizio, Simone M.Tesolin, FrancescoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner 1-gen-2023 Buccoleri, FDartizio, SMTesolin, FSanticcioli, ACherniak, DBertulessi, LBevilacqua, ASamori, CLacaita, ALLevantino, S +
4.3 A 76.7fs-lntegrated-Jitter and −71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, Simone M.Tesolin, FrancescoCastoro, GiacomoBuccoleri, FrancescoRossoni, MicheleCherniak, DmytroBertulessi, LucaSamori, CarloLacaita, Andrea L.Levantino, Salvatore +
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering 1-gen-2023 Dartizio, SMTesolin, FCastoro, GBuccoleri, FRossoni, MCherniak, DSamori, CLacaita, ALLevantino, S
Mostrati risultati da 1 a 19 di 19
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