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Mostrati risultati da 1 a 20 di 174
Titolo Data di pubblicazione Autori File
Reduction of fault detection costs through testable design of sequential architectures with signal feedbacks 1-gen-1993 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Reduction of fault detection costs through a BDD formalism 1-gen-1994 FERRANDI, FABRIZIO
ALADIN: a multilevel testability analyzer for VLSI system design 1-gen-1994 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Towards WSI testable devices: an improved scan insertion technique 1-gen-1995 BOLCHINI, CRISTIANAFERRANDI, FABRIZIOSCIUTO, DONATELLA +
Data-path testability analysis based on BDDs 1-gen-1995 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
A Wafer Level Testability Approach Based on an Improved Scan Insertion Technique 1-gen-1995 BOLCHINI, CRISTIANAFERRANDI, FABRIZIOSCIUTO, DONATELLA +
BDD-based testability estimation of VHDL designs 1-gen-1996 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Symbolic optimization of FSM networks based on sequential ATPG techniques 1-gen-1996 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Test generation for networks of interacting FSMs using symbolic techniques 1-gen-1996 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Implicit test sequences compaction for decreasing test application cost 1-gen-1996 FERRANDI, FABRIZIO +
Testability analysis of pipelined data paths 1-gen-1996 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Testing Core-based Digital Systems: a Symbolic Methodology 1-gen-1997 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Application of a testing framework to VHDL descriptions at different abstraction levels 1-gen-1997 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
How an ''evolving'' fault model improves the behavioral test generation 1-gen-1997 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Configuration-specific test pattern extraction for field programmable gate arrays 1-gen-1997 FERRANDI, FABRIZIO +
Property verification in the design of telecom applications 1-gen-1997 FERRANDI, FABRIZIO +
VHDL testability analysis based on fault clustering and implicit fault injection 1-gen-1998 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Implicit test generation for behavioral VHDL models 1-gen-1998 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Power estimation of behavioral descriptions 1-gen-1998 FERRANDI, FABRIZIOSCIUTO, DONATELLA +
Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits 1-gen-1998 FERRANDI, FABRIZIO +
Mostrati risultati da 1 a 20 di 174
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